1. Field of the Invention
The present invention relates to a semiconductor device and a designing method thereof, and particularly relates to a semiconductor device including a plurality of wiring layers and a designing method of the semiconductor device.
1. Description of Related Art
A semiconductor device is typically designed by combining a plurality of needed standard cells to lay out circuit blocks having desired functions on a semiconductor substrate (see Japanese Patent Application Laid-open No. 2009-206402). “Standard cells” refer to pre-registered layouts of logic circuits having basic functions, such as an inverter circuit and a NAND gate circuit. Wirings for connecting constituent elements in each of the standard cells and those for connecting the standard cells are formed on a plurality of metal wiring layers that are positioned on upper layers than a gate wiring layer.
If a first wiring layer, a second wiring layer, and a third wiring layer are provided in this order from below as an example of the metal wiring layers, wirings extending, for example, in an X direction are mainly formed on the first and third wiring layers, and wirings extending, for example, in a Y direction are mainly formed on the second wiring layer. In this case, the wirings formed on the first wiring layer intersect those formed on the second wiring layer, and the wirings formed on the second wiring layer intersect those formed on the third wiring layer.
If the wirings intersect one another between adjacent wiring layers, parasitic capacitances are generated in intersection regions. Because these parasitic capacitances possibly degrade signal transmission characteristics, it is necessary to reduce the parasitic capacitances depending on the types of signals to be transmitted. Japanese Patent Application Laid-open No. 2003-216063 describes a method of reducing an intersection area by providing a notch in one of intersecting wirings and thereby reducing a parasitic capacitance although this technique relates to a flat display and not to a semiconductor device.
However, because the technique described in Japanese Patent Application Laid-open No. 2003-216063 relates to a flat display, the layout of wirings and elements are accordingly determined and therefore it is easy to design the positions of notches, the sizes, and the like. In a semiconductor device, particularly in a semiconductor device using standard cells, in contrast, the layout of wirings and elements greatly differ depending on required circuit functions, characteristics, and the like, and therefore it is difficult to simply apply the technique described in Japanese Patent Application Laid-open No. 2003-216063 to such a semiconductor device. Particularly, a power supply is sometimes intensified by using meshed power supply wirings in the semiconductor device. In this case, because the power supply wirings are additionally formed so as to fill vacant spaces in which no other wirings are formed, unintended large parasitic capacitances are sometimes generated in signal wirings.